Why do we define clock uncertainty in synthesis ?

Hi

My question is : why do we define clock_setup_uncertainty, clock_hold_uncertainty during synthesis ? Shouldnt this be done in CTS only ?

Thanks

We should make sure timing is clean when clock is ideal but uncertainly is considered in order to closer the real case.

As far as I know, there are 3 components included as part of uncertainty.

Uncertainity = Base uncertainity + Clock jitter + Skew

base uncertainity : This comes in from the technology/fab. When the cells are characterized, they are not 100% sure if the values characterized are exact, so for any change/variation which can be there has to be accounted so a number is considered.

Clock jitter : The clock generating unit is supposed to give a perfect clock, but in reality there could be some shift in the edges, this has to be accounted during timing, so the number usually from the clock generating unit spec is considered here.

Skew : In Synthesis the clock is ideal, but when it goes to layout and comes with the CTS, then we have skew coming into picture, so to account for the skew a number usually (expected skew limit) is considered here.

Please correct/add information appropriately.

Hi Fahum,

Synthesis is the step in which more optimization happens so we over constrain our clock as that time so that DC can optimize more. As you will be aware of the fact that during synthesis time no physical data is there so by defining these things we try to realize real things during synthesis it self.

During pre CTS we have uncertainity defined as = Skew + jitter

but after CTS we have uncertainity defined as = Skew

as told by mvasath also

thanks
Kirtesh

Thanks all you greatly helped me

Synthesis has two major objectives - change RTL to Gate level netlist and optimize it to meet the requirements about the area, timing anf congestion or else again die size area has to be estimated. Synthesis tools have two very powerful commands -> compile & compile_ultra. this is what makes a dirty netlist into an optimized one. But on what basis can you ask the tool to optimize the timing in Synthesis stage if you don't have the clock propagated and the skew is not known. You can only estimate it and that's what we do with the uncertainty and latency constraints. We inform the tool to optimize according to numbers we provide.

Agreed with above comments , uncertainty is basically to cover clock skew and jitter tolerance in design, since at synthesis level, there is no information about clock tree timing but tool still have to work on close timing at given frequency. this uncertainty number help tool to build a timing model for clock and based on that tool calculate timing between the paths.

at STA, tool will have information about the clock tree, so there is no need to give clock skew constraint but still will have to provide clock jitter information which depend on real chip conditions.

Rahul