Why Do Negative Delays Occur in Timing Reports and What Do They Mean?

[edadl]

Hello everyone,

I have been analyzing a timing report generated by Cadence Innovus, and I noticed that some nets show negative delays.
I'm unsure about the exact reasons.
Could someone please explain why these negative delays occur in the timing analysis?

innovus 255> report_timing -from ctrl_U13/Y -to dpath_b_mux_U15/A1 -net -fall
###############################################################
# Generated by: Cadence Innovus 18.16
# OS: Linux x86_64
# Design: gcd
# Command: report_timing -from ctrl_U13/Y -to dpath_b_mux_U15/A1 -net -fall
###############################################################
#
# Timing Analysis:
# Analysis Mode : onChipVariation
# CPPR : on
# Latch Slack Mode : max_borrow
# Clock Propagation : sdcControl
# Delay Calculation:
# Engine : default
#
###############################################################
Path 1: MET Setup Check with Pin dpath_b_reg_out_reg_2_/CLK
Endpoint: dpath_b_reg_out_reg_2_/D (v) checked with leading edge of 'clk'
Beginpoint: ctrl_state_out_reg_1_/QN (v) triggered by leading edge of 'clk'
Path Groups: {clk}
Analysis View: curAna
Other End Arrival Time 4.100
- Setup 8.756
+ Phase Shift 390.000
+ CPPR Adjustment 0.000
= Required Time 385.344
- Arrival Time 265.900
= Slack Time 119.444
Clock Rise Edge 0.000
+ Clock Network Latency (Prop) 3.500
= Beginpoint Arrival Time 3.500
+----------------------------------------------------------------------------------------------------------------------------------+
| Pin | Edge | Net | Cell | Delay | Arrival | Required |
| | | | | | Time | Time |
|--------------------------------------+------+---------------------------+-------------------------+---------+---------+----------|
| ctrl_state_out_reg_1_/CLK | ^ | clk | | | 3.500 | 122.944 |
| ctrl_state_out_reg_1_/QN | v | ctrl_state_out_1_ | DFFHQNx1_ASAP7_75t_R | 107.300 | 110.800 | 230.244 |
| placeOPT_FE_OFC11_ctrl_state_out_1/A | v | ctrl_state_out_1_ | HB1xp67_ASAP7_75t_R | -7.900 | 102.900 | 222.344 |
| placeOPT_FE_OFC11_ctrl_state_out_1/Y | v | FE_OFN11_ctrl_state_out_1 | HB1xp67_ASAP7_75t_R | 59.200 | 162.100 | 281.544 |
| ctrl_U13/A | v | FE_OFN11_ctrl_state_out_1 | NOR2x1_ASAP7_75t_L | 3.500 | 165.600 | 285.044 |
| ctrl_U13/Y -> | ^ | req_rdy | NOR2x1_ASAP7_75t_L | 31.400 | 197.000 | 316.444 |
| dpath_b_mux_U15/A1 -> | ^ | req_rdy | AO22x1_ASAP7_75t_SRAM | -2.600 | 194.400 | 313.844 |
| dpath_b_mux_U15/Y | ^ | dpath_b_mux_out_2_ | AO22x1_ASAP7_75t_SRAM | 51.900 | 246.300 | 365.744 |
| dpath_b_reg_U3/A1 | ^ | dpath_b_mux_out_2_ | OAI22xp33_ASAP7_75t_R | 0.000 | 246.300 | 365.744 |
| dpath_b_reg_U3/Y | v | dpath_b_reg_n4 | OAI22xp33_ASAP7_75t_R | 23.400 | 269.700 | 389.144 |
| dpath_b_reg_out_reg_2_/D | v | dpath_b_reg_n4 | DFFHQNx1_ASAP7_75t_SRAM | -3.800 | 265.900 | 385.344 |
+----------------------------------------------------------------------------------------------------------------------------------+

 

[BradtheRad]

Negative delay makes me think 'advance'. Maybe the report recommends that you advance the timing of something that usually ought to be delayed?