[SOLVED] Why do false paths exist?

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Well the timing engine did not check if the paths are true. I means, the tool only sums the delay on the path between one flop to oneother flop, and the longest is the worst path, and as example if the same signal is connected to two AND gates of this path and require opposite value to allow the path to be active, the tools (include STA) do not check that.
STA has a additional option for the report_timing "-true_path", but the tool need to find a valid value for all inputs of all cells which involves in the path, that are very-very- time consumming.
For a design with 100kGate equivalent, Primetime was never able to return a path after 6hours of working.
 

Hey, thanks for replying.

But what I meant was why the path exist, not why it is reported. Why does it exist on the gate level netlist? Why does the logic synthesizer builds such a path?
 

A false path can originate from something that is static (non-changing) for some reason. For example, the address a chip decodes might be configurable using external pins which are pulled up or pulled down. The timing paths that these pins contribute to a logic cone are not relevant since they do not change. Hence, if we are not making timing it is prudent to mark these as false paths so that the tool will work on optimizing things that do change.
 
Hi! Yes, that is true. But it is not related with my question... this is a different type of false path.

I still did not understand why would the logic synthesis create a netlist with a logic path that will never happen, for *any* combination of stimulus. An example of what I'm saying would be:

 

That circuit was an artificial case to demonstrate what is meant by a false path. I doubt there are any synthesis tools that will produce the above circuit, they would instead remove the first mux and attach C directly to the second mux, along with a warning in the synthesis report about removing the signal B and the first mux.
 

Yikes. Based on the description on your link, the multiplexer with output D and the port/signal B should have been optimized away during synthesis.

What tool created that? Submit it as a bug.
 

No tool created that, it is just a basic example for people to understand the concept. But if we expand that concept to a complex circuit, it will happen? Or are you saying that false paths that are not sensitized by any input vector do not exist?
 

You are not helping people by showing a bogus example. No quality synthesis tool will produce your example.

So restating your original question, "Why does this particular false path exist?". The answer is false paths of this type do not exist.

Maybe you should do a web search of false paths and so you get a better understanding of them.
 

Well, I found this example while doing a web search of false paths... as I said, I think it fits okay to explain the principle.

So, my question is not if that particular false path would exist. My question is if false paths that are not sensitized by any input vector do exist.

Thanks!
 

If an input to a logic cone doesn't contribute (result in a change of state) to the output then the synthesis tool should optimize the input away. Only by forcing the synthesis tool to not optimize the signal away will you have such a case.

The typical false path case was explained in post #4.

Regards
 
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