matrixofdynamism
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Digital designs often need multiple clock domains. I once heard of a design that had more than 10 clock domains on a very large FPGA.
One case I have seen of needing multiple clock domains was when I had to use a DDR3 controller in Platform Designer for a design that targeted Intel FPGA.
One more case I came across is where the FPGA was implementing a communication protocol stack and the part that interfaced with the physical medium had to run at a certain frequency for the receiver electronics on the other side to work correctly. In these cases, something outside the FPGA forced the design to contain multiple clock domains.
However, lets assume that there is no external component that forces such a requirement. Why would one need to have multiple clock domains in that case? Does it still happen?
One case I have seen of needing multiple clock domains was when I had to use a DDR3 controller in Platform Designer for a design that targeted Intel FPGA.
One more case I came across is where the FPGA was implementing a communication protocol stack and the part that interfaced with the physical medium had to run at a certain frequency for the receiver electronics on the other side to work correctly. In these cases, something outside the FPGA forced the design to contain multiple clock domains.
However, lets assume that there is no external component that forces such a requirement. Why would one need to have multiple clock domains in that case? Does it still happen?