Why do digital designs often need multiple clock domains?

[matrixofdynamism]

Digital designs often need multiple clock domains. I once heard of a design that had more than 10 clock domains on a very large FPGA.

One case I have seen of needing multiple clock domains was when I had to use a DDR3 controller in Platform Designer for a design that targeted Intel FPGA.

One more case I came across is where the FPGA was implementing a communication protocol stack and the part that interfaced with the physical medium had to run at a certain frequency for the receiver electronics on the other side to work correctly. In these cases, something outside the FPGA forced the design to contain multiple clock domains.

However, lets assume that there is no external component that forces such a requirement. Why would one need to have multiple clock domains in that case? Does it still happen?

 

[dave_59]

It's used to conserve power. Not all functionality needs the same clock rate to meet timing.

 

[dick_freebird]

You might have multiple same-frequency, different-phase
clocks recovered / reconstructed from serial data input,
whose exact timing is independent of your master clock.
Each of those is its own domain until you "bring it on
board" through some synchronizing logic.

 

[KlausST]

Hi,

you say "not coming from an external signal".

So generated inside:
* You may use internal PLL/VCO to generate a modulated RF signal for data transmission
* You may use 2 internal PLLs to generate two (slightly) different frequencies for dedicated undersampling (ADC)
* You may use a PLL to generate a spread spectrum clock

* Usually I call clocks generated by a divider: to be within the same clock domain ... unless you use them as a true new timing reference.

Klaus