why DLL fails to lock when Tdmin<0.5*Tref or Tdmax&am

[sanjaytamne]

DLL false locking

Hi,

I want to know why conventional DLL fails to lock when Tdmin<0.5*Tref or Tdmax>1.5*Tref.
Your help is appreciated.

 

[sudheerkm]

Re: DLL false locking

its because ur phase detector ouput will be at rails

 

[sanjaytamne]

Re: DLL false locking

Thank you for reply...
But I have a doubt...
Whether the delay is slightly less than 0.5*Tref or slightly greater than 0.5*Tref, in both the cases my PFD will generate UP pulses, as falling edge doesn't have any effect on the operation of PFD. In both the cases it will try to reduce delay. Then how does it will lock if delay>0.5*Tref & <Tref ?

 

[dick_freebird]

Re: DLL false locking

If your detector responds only to phase, and your period is
exactly half, you can still get phase-match (just every other
edge). Similarly if your period is 2, 3, ...X. Perhaps a phase-
frequency detector would fix that.