EDA_hg81
Advanced Member level 2
The attachment is my simulation figure.
The question is when the Vss is 3.3V the voltage at “in2” node is 12mV, but why voltage at "out" node is 12mV too?
I think diode is going to block this 12mV and voltage at “out” node should be 0V.
So many thinks for any ideas.
[/i]
The question is when the Vss is 3.3V the voltage at “in2” node is 12mV, but why voltage at "out" node is 12mV too?
I think diode is going to block this 12mV and voltage at “out” node should be 0V.
So many thinks for any ideas.
[/i]