Why designers write VHDL codes which include UNISIM components?

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go4sandesh_vsn

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hi all...

i've observed some of the designers write their VHDL codes including UNISIM components directly...
Can anyone tell me why they do so...n how much helpful this could be n in wat sense.....

I really cudnt figure it out reason for UNISIM library inclusion other than in cases where u really need to instantiate some components like FIFOs (using template) or buffers....
n i believe Unisim lib inclusion is not required if u dont hav anything to instantiate...m i right??????
 

Re: regd VHDL n UNISIM

Hi go4sandesh_vsn,

as far as i know, unisim lib comes from xilinx.
So whenever you want to use xilinx core in your fpga, you can use unisim lib instantiate component used in your design (as described in your fpga manual).
Then when it comes to synthesis stage, xilinx tool will use the corresponding core for your component (e.g. FIFO, Multiplier, etc.).

Yes you are right you dont need unisim if you dont use any built-in component.
But o fcourse, you can always use components in unisim for your behavioural simulation, but it does not make sense if your fpga does not have that core.
I hope that it helps.
rgds.
 
Re: regd VHDL n UNISIM

Hi,

Basically Unisim contains simulation models of Xilinx internal elements.

They are used to get exact behaviour of the elements as these will be then mapped during synthesis.

Thanks,
Gold_kiss
 
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