why CT DSM ADC more sensitive to clk jitter then DT DSM ADC??

Hi all,

Does anyone know why CT DSM ADC more sensitive to clk jitter then DT DSM ADC??

My understand is for CT DSM ADC, at outmost feedback DAC output, quantization noise will mix with jitter then fold back to passband. But that should apply to DT version too, right?

Thanks
gggould

Hi
Jitter is caused by the error introduced in the feedback DAC of the first integrator due to clock edge uncertainty. In discrete , this feedback DAC is implemented using switched-capacitor. First a cap is charge to some potential Vref and then discharged into the first integrator. This capacitor will discharge with an exponential decaying shape. Now at the edge of the clock period, the value of this pulse would have reduced to a much smaller value (typically 10-12 time constants are there in one clock period. So if there is any uncertainty in the clock edge, very small error will be added because the feedback current has decayed to a very small value.

In CTDSM, the feedback pulse is typically constant throughout the clock period. So any jitter in clock leads to a much larger error. This makes CTDSM more prone to jitter problems. It is possible to implement the feedback DAC like a switched capacitor, in which case even CTDSM will be less prone to jitter, however some of its benefits will be compromised.

Thanks for the comment. So basically the extra jitter sensitivity for CT is mainly due to excess T_j*V_dac compared with DT counterpart, but not really quantization noise folding to passband ?

gggould said:

Thanks for the comment. So basically the extra jitter sensitivity for CT is mainly due to excess T_j*V_dac compared with DT counterpart, but not really quantization noise folding to passband ?

Click to expand...

Yes that is correct. Chapter 5 of this thesis has a very good analysis of jitter in CTDSM

Thanks a lot!!