why clock inverters are preferred over clock buffers in CTS?

[coolrak]

duty cycle inverters and buffers

Hi everybody,

I would like to know why clock inverters are preferred over clock buffers in CTS stage.

thanks in advance

 

[tarkyss]

i think the reason maybe the delay of the inverter is smaller than a buffer,
so, the clock skew maybe smaller(of course you can insert buffer in other path to balance the clock skew, but i will cause extral area and power consumption)

 

[eda_wiz]

as tarkyss said inverter delay is lesser than buffer for the same drive capacity. buffer is basically 2 inverters connected back to back. so the insertion delay [modelled by set_clk_latency in DC]of the clock tree will be lesser.

hope it helps
EW

 

[cdic]

Re: why clock inverters are preferred over clock buffers in

maintain duty-cycle.

 

[coolrak]

Re: why clock inverters are preferred over clock buffers in

Thanks tarkyss and eda_wiz. My doubts got cleared

 

[ivlsi]

Re: why clock inverters are preferred over clock buffers in

maintain duty-cycle.

Why inverters on the Clock Tree maintain Duty Cycle and the regular buffers don't?

 

[jeevan.life]

Re: why clock inverters are preferred over clock buffers in

Why inverters on the Clock Tree maintain Duty Cycle and the regular buffers don't?

Clock buffers and clock inverters are usually built to maintain uniform duty cycle. The main difference is in the area where buffer uses a higher area to drive a signal to certain distance before it has to be rebuffered. If inverters are used , you can drive the signal to the same distance with almost half the number of cells.

 

[ivlsi]

you can drive the signal to the same distance with almost half the number of cells.

Did you mean "half the number of transistors"?

 

[beowulf]

Re: why clock inverters are preferred over clock buffers in

Clock buffers and clock inverters are usually built to maintain uniform duty cycle. The main difference is in the area where buffer uses a higher area to drive a signal to certain distance before it has to be rebuffered. If inverters are used , you can drive the signal to the same distance with almost half the number of cells.

One basic question: Why is it important to have a 50% or uniform duty cycle for the clock...?
Thanks,
Beo

 

[faizalism]

Re: why clock inverters are preferred over clock buffers in

It depends on your design...for practicality better if we can make sure the duty cycle ~40-60% to accommodate positive and negative edge trigger.

 

[kumar_eee]

I didn't understand why the duty-cycle comes into picture here. Can anyone elaborate please?