Why cant you jog in lower metal for antenna effect

[raghurama86]

Hello friends,

I have a lots of doubt in antenna violation why we dont route in lower metal layers,

I have someone please let me know if my analysis is right,

The main intention to avoid antenna violation is to break the metal layer either it is lower or higher it should not matter, cause once a lower layer fabrication is done the charges accumilated on that metal is removed so there should not be any addition of charges once next metal is routed.

assuming this is true

next thing is tool algorithm I feel the tool will check for the antenna violation layer by layer (ie M1 then M2 then M3 so on)

if we have a violation in M4 and if the tool jogs to M5 still if the routing is large on M5 the tool will catch violation in M5 but if it goes down to M3 the tool will have to begin analysis from M3 and if it still goes down to M2 the analysis must start from M2 this might take a big hit on runtime and the tool might not converge at all, I feel this is the reason for the tool to always jog on higher metal layers, can some on please tell me if this is true


I saw in the forum that lower metal joging in not done because of higher resistance of the layer, but if net is not timing critical net does it mean that the tool can still go dome to lower metal?

thank you

 

[rca]

the tool check antenna by adding the wire length on each metal that's drive the gate, and the techno lef provide the antenna factor for each metal, and the std cell LEF provides the maximum charge acceptable by this inputs.

So the tool does not check layer by layer, but net by net.

 

[randyest]

As rca said, the tools tend to check net by net, not layer by layer.

The reason you have to jog up and not down is because of the order in which layers are added. Basically, I don't think this is true:

"use once a lower layer fabrication is done the charges accumilated on that metal is removed so there should not be any addition of charges once next metal is routed. "

How do you expect the charge to be removed? Where does it go?

 

[raghurama86]

hi randyest,

I said I am assuming they will remove charges .. cause I felt if X ammount of charge in 1 metal can destroy the gate then x ammount of charges in n number of metal layers connected together should also destroy the gate,

I think they route metal 1 somehow remove the charges then metal 2 so that the charges will not add up. that is what I felt I know it is not logical to remove the charges but I could not convince me with a better answer.

can you explain why cummilative effect of carges on the metal does not destroy the gate?


Thank you

 

[randyest]

**broken link removed**
**broken link removed**
Semiconductor mfg uses charged plasma or wet-type stripping to build up each layer from bottom to top. Both ways put charge on the metal wire being made (charged plasma or electrostatic charge.) I think you understand this part.

The connection to the gate is at the lowest level, usually POLY. In general a short wire won't accumulate enough charge to damage the gate. The charge flowing into the gate is proportional to the area of the metal exposed to the charged plasma. (Area of top-surface of wire OR side surface of wire OR both) / (Area of gate insulating film). The details of what is "short" enough to be OK depend on the metal type (Cu or Al) and the exact mfg process.

You can see in the attached pictures that if a long wire is connected to the gate, but is not connected to diffusion layer, there is no place for the charge to go except through the gate. Enough charge can destroy the gate or reduce reliability. But if there is jog up to top-layer of metal near the gate, then when the long metal is made, there will also be a connection to diffusion that the charge can safely go to instead of the gate. So only a small charge is on the gate because only a small wire is connected to it. When the long wire is made, it is also connected to diffusion.

I hope that is clear for you.

 

[raghurama86]

Yup it is clear thank you

 

[arjun1110]

Hi Randyest,

In antenna2.png, second diagram(Still antenna error) near the diffusion if i connect with lower layer(like how it is connected near the gate) still there will be any antenna error?

 

[lostinxlation]

Hi Randyest,

In antenna2.png, second diagram(Still antenna error) near the diffusion if i connect with lower layer(like how it is connected near the gate) still there will be any antenna error?

No antenna errors in that case because as soon as the gate gets connected to a long metal with big capacitance, it has full connection to diffusion which provides the charges with the escape path.