The initial statement is not synthesizable.please write a code with the initial statement and try to convert that statement into the gates then u will know the ans.
regards,
ramesh.s
ASIC flipflops do not have a built-in power-on/initialization circuit. This circuitry must be designed and implemented manually. Therefore, most ASIC synthesis tools cannot handle the 'initial' statement.
FPGAs work a little differently. The "power-on" state is defined as the moment right after FPGA-configuration cycle finishes. This means the 'power-on' state can be stored in the configuration-bitstream. And Xilinx XST supports the Verilog "initial" block (and VHDL attribute) for setting power-up value of flipflops.
initial statement is used to initialise any i/p value from where the simulation has to start.
if we donot use initail value in our test bench.. then the initial value of input will be taken as dont care and o/p will be also dont care.