Lower metal levels impact cell library and close-in routing
density so lithography there values fine pitch. Etch process
control at fine pitch wants a thinner layer, side-etch is a
control problem made worse by layer thickness / height.
Planarity also is helped by thinner lower layers, less work
for the CMP planarization steps.
A competing interest is having high current carrying capacity,
low series resistance and, for RF, low stray capacitance.
The first two are had by thicker metal, the latter by having
the layer higher above the substrate plane. Assuming you
want all these things, you do it at the uppermost one or two
levels, and you take the pain of increased minimum line width,
increased spacing.