luodong
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Hi All,
When I do hold time analysis after P&R using PrimeTime, I find a phenomenon that there are usually more hold time violations in best corner than in worst corner for the same design. I don't understand why this phenomenon exists.
Let's assume the clock slew of the design is 0 to simplify the topic to be discussed. And assume the delay that is from launch flip-flop's clock pin to capture flip-flop's data input pin is A in worst corner and is B in best corner. Assume the hold time limit of the capture flip-flop's data input pin is C in worst corner and is D in best corner.
In my option, if a path's hold time slack is greater than 0 in worst corner, that means A > C. When I do hold time analysis for the same path in best corner, of course, both the delay from launch flip-flop's clock pin to capture flip-flop's data input pin and the hold time limit of the capture flip-flop's data input pin become smaller than the values in worst corner, I think we can assume B = k1*A and D = k2*B. Of course, both k1 and k2 are greater than 0.0 and less than 1.0. I think the values of k1 and k2 may not exactly identical but they probably close to each other. So B is probably greater than D. So there should not be more hold time violations in best corner than in worst corner. For my understanding, can anyone explain which part is wrong?
If k1 is usually much smaller than k2 which leads to more hold time violations in best corner than in worst corner, can anyone explain why k1 is usually much smaller than k2? Thanks.
When I do hold time analysis after P&R using PrimeTime, I find a phenomenon that there are usually more hold time violations in best corner than in worst corner for the same design. I don't understand why this phenomenon exists.
Let's assume the clock slew of the design is 0 to simplify the topic to be discussed. And assume the delay that is from launch flip-flop's clock pin to capture flip-flop's data input pin is A in worst corner and is B in best corner. Assume the hold time limit of the capture flip-flop's data input pin is C in worst corner and is D in best corner.
In my option, if a path's hold time slack is greater than 0 in worst corner, that means A > C. When I do hold time analysis for the same path in best corner, of course, both the delay from launch flip-flop's clock pin to capture flip-flop's data input pin and the hold time limit of the capture flip-flop's data input pin become smaller than the values in worst corner, I think we can assume B = k1*A and D = k2*B. Of course, both k1 and k2 are greater than 0.0 and less than 1.0. I think the values of k1 and k2 may not exactly identical but they probably close to each other. So B is probably greater than D. So there should not be more hold time violations in best corner than in worst corner. For my understanding, can anyone explain which part is wrong?
If k1 is usually much smaller than k2 which leads to more hold time violations in best corner than in worst corner, can anyone explain why k1 is usually much smaller than k2? Thanks.