Why are mealy FSMs not so common?

[ricksanchez]

Why are mealy FSMs not so common?
I am in a situation where I cannot avoid using it . I have a signal which determines the state of my FSM and also the same signal(without any delay) determines the output.
will it create any problem in STA?

 

[FvM]

Mealy establish a combinational path from input to output signals. Safe state machine design rules suggest that all input signals either originate from the FSM clock domain or are synchronized to it. If so, Mealy output signals can be processed in the same clock domain without problems, except for having probably a larger path delay.

If the output is used asynchronously or transferred to other clock domains, signal glitches come into view.