Nails
Newbie level 1
de1 sdram 100mhz
Hi,
I am trying to analyze the layout and construction of an Altera DE1 development board, because I want to make a board similar to it.
I have determined that it is a 6 layer board with the following layer stackup based upon grinding down the side of the board to reveal the copper layers, and probing to know VCC and GND signal test points. Details on inner layers were gleaned by trying to route an idential circuit from the assigned FPGA pins to the SRAM, and using the same via's and placement of the SDRAM.
1 - signals
2 - signals (always only crossing layer 1 signals at a 45 or 90 degree angle, never in parallel)
3 - gnd
(large core here between gnd and vcc)
4 - vcc
5 - signals (only a few)
6 - mainly a gnd plane, but a few signals are routed into it.
However, upon reading almost everything I can about layer stackups, this is a stackup that is rarely recommended. The most common one is:
1 - signals
2 - gnd
3 - signals
(large core here)
4 - signals
5 - vcc
6 - signals
Using this method seems much more preferable as you don't have the problem of running traces on signal layers 1 & 2 at an angle to each other. Also, high speed signals and clocks can be on inner layers and shielded.
So what would be the advantage to constructing the board the first way and have to go through extra routing trouble to avoid cross-talk in signals on layers 1 and 2? Is this advantage a big deal?
I am stumped...I actually found one board reference design that suggested to lay things out this first way, but I can not find it now. 99% of all other reference designs say to do the layer stackup the second way.
Does it really matter when you are only running around 100 Mhz?
The only thing I can think of is there might be some manufacturability reasons because of the numerous tiny via holes. ???
Any insight would be greatly appreciated.
Thanks.
Hi,
I am trying to analyze the layout and construction of an Altera DE1 development board, because I want to make a board similar to it.
I have determined that it is a 6 layer board with the following layer stackup based upon grinding down the side of the board to reveal the copper layers, and probing to know VCC and GND signal test points. Details on inner layers were gleaned by trying to route an idential circuit from the assigned FPGA pins to the SRAM, and using the same via's and placement of the SDRAM.
1 - signals
2 - signals (always only crossing layer 1 signals at a 45 or 90 degree angle, never in parallel)
3 - gnd
(large core here between gnd and vcc)
4 - vcc
5 - signals (only a few)
6 - mainly a gnd plane, but a few signals are routed into it.
However, upon reading almost everything I can about layer stackups, this is a stackup that is rarely recommended. The most common one is:
1 - signals
2 - gnd
3 - signals
(large core here)
4 - signals
5 - vcc
6 - signals
Using this method seems much more preferable as you don't have the problem of running traces on signal layers 1 & 2 at an angle to each other. Also, high speed signals and clocks can be on inner layers and shielded.
So what would be the advantage to constructing the board the first way and have to go through extra routing trouble to avoid cross-talk in signals on layers 1 and 2? Is this advantage a big deal?
I am stumped...I actually found one board reference design that suggested to lay things out this first way, but I can not find it now. 99% of all other reference designs say to do the layer stackup the second way.
Does it really matter when you are only running around 100 Mhz?
The only thing I can think of is there might be some manufacturability reasons because of the numerous tiny via holes. ???
Any insight would be greatly appreciated.
Thanks.