[SOLVED] why a Flip Flop based ASIC design not a LATCH based design

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praneethrajkanakam

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Hi..

why not Latch based ASIC design is not prefered when compared to Flip Flop

As Latches are faster than Flip Flop.
 

How would you time your design if you use Latches instead of flip flops?
 

There are two main problems with latches
a) time borrowing is advantageous but it has a ripple effect. the timing aspect is something which needs to be tweaked in the STA tools to handle latches. This is much tougher than it seems.
b) Testing : the DFT scan insertion tools cannot handle latches automatically. THIS IS BY FAR THE BIGGEST PROBLEM with latches.
having said that latches are used in high speed blocks : Timing is done through two phase clocks and testing is done through BIST(which has area overhead).
 
There are chips designed mostly with latches. There are special ways to handle STA. Due to NDA, I can't elaborate it.
Generally, Latches are used for extremely power/area sensitive designs.
 
there can be latches used in designs but it has issues as with ASIC(I think that was the posting)....Most of the ASICs relying on static timing analysis...
Asics like Arm processors in phones rely flops mainly
server chips ....use latches with customized clock tree/DFT ..... but I don't agree with power because latch based designs are good for speed but at the end of the day they consume more power.
 
You are right in "most" of the ASIC relying on STA. But not all ASIC chips are designed based on flops.
For your opinion of latch being good for speed and not for power, I can only say that the chip I designed(and manufactured) with latches is not at all for speed. It is indeed designed with power-saving as the highest consideration.
Trust me or not. That's all I can say.
 
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