about mc6805
Here's the first two pages translated from Spanish, courtesy of WorldLingo.
**broken link removed**
hope it helps some.
*gado
1. Introduction
The use of embedded sequential processors
within complex designs it is an alternative
of habitual use when, along with a task of
high performance, it is necessary to take care of
applications of low speed andor complexity
algorítmica so that they make advisable certain
type of sequential processing.
The 10 nowadays solutions that are [ ]
they are different in two great groups:
· simple microcontrollers: of the type
6805[8 ], 6502 or 8051[1 ], or similars, whose
more important comparative advantage is
little use of resources, and whose application
typical it is the interphase to the user or others
applications of low speed like
keyboards, displays, or communication mouths
asynchronous. In all the cases they are designs
that they are compiled next to the design of the user
("soft-cores").
· processors of high performance: like
NIOS[4 ], ARM[2 ], MIPS [ 3 ], oriented a
tasks of complex processing, of discharge
performance, that they consume important
amount of logical resources. Whereas
processor NIOS is soft-Core as much
ARM as MIPS corresponds a
hardware solutions that offer
processor predefined already wiring in
dice chip ("hard-Core").
The serial design adapts specially to
design of simple microcontrollers, then
it diminishes in important form
requirements of ruteado (connections and keys)
at the cost of requiring several cycles of clock by
each byte that is transferred; nevertheless, this
temporary penalty is less and less
important thanks to the high speed of
clock that tolerates the new families of logic
programmable. As well, the smaller exigency of
resources of conexionado makes possible to distribute
design throughout a chip and to take advantage of
hollows that the system of Place&Route has
left when rutear the discharge stages free
performance.
The commitment of design between speed of
operation and use of resources of conexionado no
it happens only within the area of the logic
programmable: for example, the family of
microcontroller of Harvard architecture
modified COP8SAx de National [ 11, 12, 13]
it operates with a clock of 10MHz, at the rate of
instruction cycle each 10 cycles of clock, and
although its operation does not present/display differences
with the one of other devices of 8 bits where
processing is in parallel, internally
operation is serial (in each instruction cycle
the serialización of 8 bits is made).
diminution of the ruteado complexity of and
smaller amount of lines than exchanges
simultaneously it determines that these
processors are economic and generate
a level of electromagnetic interference
(EMI) until 20dB smaller to the one of processors
similars operating to equal number of MIPS.
Another interesting example is the one of
Transputers, where the use of connections series
(Serial Links) between processors it facilitates
connectivity [ 15 ].
This article presents/displays certain general concepts of
design of 6 seriales processors [ ] and analyzes
architectonic advantages of the family
FLEX10K[5 ] of ALTERS for this type of
designs, taking as particular case for
certain examples functional modules of
processor COP8SAx type. In addition, it looks for
to show how through a careful design
that it considers the characteristics of the family of
FPL to use, it is possible to obtain a great one
efficiency of use of resources.
2. General considerations for
design of processors
When designing a dice processor, in order to try
to arrive at an optimal design becomes necessary
to analyze the different actors from the CPU as much
(registries, memories, calculation units,
address units, modules of
decoding) like the information flow
(of instructions, data and control) required
between these actors during the execution of
possible 7 instructions [ ]. East fact analysis,
the advantages must be considered architectonic
that it offers the technology to use, having in
it tells that certain solutions comply
better than others to certain type of architectures
In a processor HARVARD type like
COP8SAx can be identified like actors a
the registries To, B, X and SP, the devices of
IOr, the memory of data (DM) and the memory of
program (PM), and certain functional blocks
necessary for decoding of instructions
(YOU GO) and generation of directions (AG). A
it differentiates from the 6805, in a COP8SAx
registries B, X, SP and the iOr they are also
addressable in the space of data.
For the interconnection of these actors they exist
several buses, each one of which it presents/displays
particular characteristics:
· the bus of program directions (PAB)
it has an only origin (AG) and an only destiny
(p.m.), and it can be of 10 to 12 bits. In one
application of FPL agrees that the wide one of
this bus is parametrizable according to
requirements of this application.
· the bus of program contents (PCB)
it has an only origin (PM) and like possible
destinies to YOU GO, to the AG, to the DAB or the DCB.
· the bus of directions of data (DAB) is
bus of 8 bits that it has like possible origins
to the p.m. (direct address), to
registries B or X (indexed addressging),
or to the SP (handling of the battery), and like possible
destiny to the DM, IOr, B, X and SP.
· the bus of data (DCB) transports
information from the p.m., To, or the space of
memory of data towards A or to the space of
memory of data. The complexity of this
information flow is given by
existence of multiple actors mappings in
this space of memory of data (multiple
origins, multiple destinies) as well as by
existence of certain instructions (XeXchange)
where two data interchange a
the time, between A and the other actor.
The internal buses of a processor can
to be solved by means of bidirectional buses and
buffers tristate or by means of multiplexors [ 7,
14], and each one of these solutions presents/displays
certain advantages and disadvantages:
· the use of bidirectional buses and
buffers tri-state diminishes the use of resources
of wiring, but it generates the risk of "buscontention"
(two exits exciting the bus
simultaneously with opposite values),
doing necessary to consider times of
it keeps and circuits of security that sometimes
they annul the wiring advantages.
· the ruteado one of unidirectional buses
by means of multiplexors it is inherently
surely, more express, and it allows certain degree of
concurrence, although at the cost of the consumption
of greater resources of wiring.
3. Considerations of design using
FLEX10K
When making the design of a device using
family FLEX10K of ALTERS must have itself in
she counts his architecture:
3.1. The logical elements (Them): they are
elementary constructive elements
("atomic") of family FLEX, and
they compose of a stage combinatoria based on
the use of tables (or LUT) of 16 bits (4 entrances)
followed of an optional registry. The reduced ones
dimensions of each HIM and the great amount of
they cause that family FLEX10K lends a
designs that make use intensive of registries.
In addition, they have the capacity to Them of
to form itself in a called way arithmetic,
where an auxiliary function called CARRY
CHAIN allows to discharge propagation efficiency
of Carry between contiguous Them for
accomplishment of sumadores, accountants or others
numerical circuits. Also they offer one
called function CASCADE CHAIN that
it allows to make the logical AND of the exits of
Contiguous them, and thus to facilitate the calculation of
certain functions of many variables (great
fan-in).
When gliding a design, and previous to go to details of
design, it agrees therefore to consider like
to obtain the maximum advantage of these
"atomic" elements.