Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Who to map modulators +/- output in VHDL?

Status
Not open for further replies.

ahmad_abdulghany

Advanced Member level 4
Advanced Member level 4
Joined
Apr 12, 2005
Messages
1,206
Helped
102
Reputation
206
Reaction score
22
Trophy points
1,318
Location
San Jose, California, USA
Activity points
11,769
According to the figure below,

If I'm going to develop a VHDL code for each of these modulators (i.e. PSK, QPSK, 16-QAM), and as it can be seen for example for the QPSK the mapped output varies between 1 and -1, and for the 16-QAM, it's further stragne as it takes values like +/-3 and so on..
How can this be mapped in a VHDL code, that only have (as far as i know) binary data (i.e. 1's and 0's)

Thanks in advance,
Ahmad,
 

Re: VHDL question

I will give a tip on +-3 issue only: Use the datatype 'real' for such numbers or binary-represent them as vectors.
 
Re: VHDL question

WM3 said:
I will give a tip on +-3 issue only: Use the datatype 'real' for such numbers or binary-represent them as vectors.

I thought in that already, but i think it can't be.. How would it be synthesized? i.e. 'real' datatype?

Anyway, thank you ..

Any more??
 

Re: VHDL question

I think i'm now very close to the solution,
WM3 was right :)
But it'll be further difficult than simply using vector, instead, i will represent the analog value (e.g. 3 or -3) interms of binary (and will be transmitted on a BUS)

I didnt' try it yet, but going with it.. I hope i succeed..

Keep on..
Thanks alot,
Ahmad,
 

Re: VHDL question

SA Ahmad,

In all cases your I and Q are buses. Even in QPSK and BPSK you are transmitting +1's and -1's not only a 1 and a 0. You have to perform level mapping as shown in the constellation diagrams you sent earlier.
In QPSK and BPSK a signed vector of 2 bit width would do, but in the 16 QAM you would need to make the I and Q buses 3 bits wide to take values up to +3 or -3.
Good luck ya gameel :)

Salam.
Ahmed M. Ragab
 
Re: VHDL question

Salam,

Raghab has suggested a good solution for the problem. you can always use signed vector to represent your real values.

Tasnif
 

Re: VHDL question

Ahmed Ragab said:
SA Ahmad,

In all cases your I and Q are buses. Even in QPSK and BPSK you are transmitting +1's and -1's not only a 1 and a 0. You have to perform level mapping as shown in the constellation diagrams you sent earlier.
In QPSK and BPSK a signed vector of 2 bit width would do, but in the 16 QAM you would need to make the I and Q buses 3 bits wide to take values up to +3 or -3.
Good luck ya gameel :)

Salam.
Ahmed M. Ragab

Wa alaykom assalaam :)
Thank you for your replies..

I have some other little questions..

Q1) Will i represent numbers in their two's complement, or sign-magnitude?

Q2) Can I assign using the decimal value and implicitely it understand the corresponding binary value (e.g. I assign value of -3 and it becomes 101 as its two's complement)

Q3) Regarding fractions that may be needed to be used in schems like 8-PSK, i will use a BUS with certain precession. If i used 8-bits will give 256 different levels, and i want them to correspond to values from -1 to 1 with fractions.. each bit or level will correspond to decimal value of 1/16=0.0625 ... i.e. the binary number 00000000≡-0.9375, 100000000≡decimal zero, and 11111111 ≡+1, and in between, values varies between these values with step 0.0625 .. e.g. 00000001≡-0.8750 and so on.. i.e. i have 127 negative values and 128 positive values and the 'zero'.
The question is, if i want to represent a number say=+0.3827 then i will divide it by 0.0625 that gives 6.1232≈+6, then the corresponding binary representation will be 10000110 . This is nither exact or simple.. if this is the correct method but there's an easier way to deal with, so please tell me..

Q4) Finally, as i want to make single block performing all types of modulation and demodulation, then use two MUXes for I and Q BUSes after mapping, to select the required scheme output, so i think i have to fix length of BUS (say 8 bits).. right?


Thank you for helping and being patient as well :)
Ahmad,
 

Re: VHDL question

for the first two questions first it is better to go for a 2s complement representation and representing the number in binary format even if they are negative.
 

Re: VHDL question

secondlife said:
for the first two questions first it is better to go for a 2s complement representation and representing the number in binary format even if they are negative.

But, using two's complement will not fit with fractional representation of numbers..right?
 

Re: VHDL question

Checkout this may help you!
**broken link removed**
 
Last edited by a moderator:
Re: VHDL question

nand_gates said:
Checkout this may help you!
**broken link removed**

Thank you, but i think the process followed there isn't accurate otherwise, i will use large number of bits to obtain good accuricy guaranteeing my requirements..
 
Last edited by a moderator:

Re: VHDL question

SA Ahmad,

I must be missing something in your questions, since I find no problem in representing negative fractions in binary form and using 2's complements.

Regarding their representation and the matter of accuracy, you may prefer using this library found at:
**broken link removed**
Check the fixed_pkg.

They are new proposed libraries to be added soon into tools. You will find a function named resize that would take in your number as a decimal fraction and convert it into the vector size you're using with the chosen precision.
Say you need to work with an 8 bit vector that would represent fractions from +1 to -1 then you would choose it to be a signed fixed number "Sfixed(0 downto -7)".
The tool would understand that you have only 1 bit before you're decimal point (which is infact your sign bit) and 7 bits after your decimal point, giving you a minimum resolution of 0.00000005.

You'll have to play a little with your libraries in order to make your tool synthesize them well.

I hope in someway I've made things clearer. If not then don't hesitate to pm me :))

Salam,
Ahmed M. Ragab
 
Re: VHDL question

I think you can use ROM for mapping your qpsk and qam.., and use it like this
address(rom)≡datainput(map) and dataoutput(rom)≡map output,and you use a mux to select betwen qam and qpsk.....MOC
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top