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for sure - many foundries have memory-generators, but normally they just propose you to generate a macrocell on demand. In most cases you can generate a VHDL- or Verilog-Model of the memory, that you can use for simulation. Some propose some tools to get a first impression of area, power consumption, etc.
Actually memory is pure analog(or transistor) level design. The delay parameters you saw in Verilog model comes from Spice simulation with actual circuit netlist plus some parasitic RC elements. So it doesn't make any sense to add any delay by yourself to any verilog memory model provided from IP vendors/foundary. If you are interesting about memory design, you may refer to the following books for your reference : )
1. CMOS Memory Circuits
By Tegze P. Haraszti
Kluwer Academic Publisher 2000
2. VLSI Memory Chip Design
By Kiyoo Itoh
Springer 2001
Actually memory is pure analog(or transistor) level design. The delay parameters you saw in Verilog model comes from Spice simulation with actual circuit netlist plus some parasitic RC elements. So it doesn't make any sense to add any delay by yourself to any verilog memory model provided from IP vendors/foundary. If you are interesting about memory design, you may refer to the following books for your reference : )
1. CMOS Memory Circuits
By Tegze P. Haraszti
Kluwer Academic Publisher 2000
2. VLSI Memory Chip Design
By Kiyoo Itoh
Springer 2001
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