Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

who can explain the zero in the frequency response

Status
Not open for further replies.

Jenifer_gao

Member level 1
Member level 1
Joined
Jun 14, 2004
Messages
38
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
552
Hi all:

I am new to the electronic design and analysis, especially for the frequency response. It always makes me headache. I vaguely know that the pole is associated with bandwith and phase margin properties, but I don't know the zero very well. What does it associate with? Why it only occurs in the left side of the complexed frequency domain.
If anyone can explain the the zero and pole in a very simple way? Thanks

J
 

Frequency responses of linear, continuous systems are in the form of a fraction with polynomials as the numerator and denominator. The roots of the denominator polynomial are called poles and the roots of the numerator are called zeros.

Roots are the complex frequency that makes the polynomial be zero.


The polynomial has angualr or cyclic frequency as the independent variable.
 

hi,
the poles determine the intrinsic form of the systems response.
the zeros determine the effect of each pole on the form of systems responce.
for example if a zero be close enough to a pole we can neglect that pole(only for left hand poles and zeros)

the poles must be in the left side of jω axis because the right hand poles unstable the system.(they produce an exponential term with positive exponent in the time domain).
but the zeros can be in the right hand.(systems with a zero on the right hand called non minimum phase.)
 
In a circuit topology, if there is more than one signal path between two nodes, there will be a zero .
BTW, I like the reply of is_razi :)
 

I'll add something else,poles of a polynomial determine the speed of the system,i mean the time until it reaches the steady-state.Zeros affect the amplitude of the responce.Poles are what make the system stable or unstable...
 

Alles Gute said:
In a circuit topology, if there is more than one signal path between two nodes, there will be a zero .
BTW, I like the reply of is_razi :)

just want to add something in that

if the signal from path1 is going to be added with signal from path2 then there will LH Zero..example source follower with significant finite cgs..
if the signal from path1 is of opposite sign than the signal from path2 then there will RH Zero..example miller compensation/common source amp with significant cgd..
 
Hi all:

Thank you all for the replys, which give me more information than I need.
The further question is realted to the zero value. When I read the book of "cmos analog circuit design" by Phillip E. Allen, there is an assumption in example 6.2-1(location of ouput pole for a phase margin of 60), which assumes that the zero is 10 times higher than GB. I don't know why the author gave such an assumption. If anybody can give me some information about the practical value of the zero in the real design.
Thanks.

J
 

When you have zero your step response can for some small time go down (become negative), and after that continues to up, like standard response...

Added after 4 minutes:

bjerkely said:
I'll add something else,poles of a polynomial determine the speed of the system,i mean the time until it reaches the steady-state.Zeros affect the amplitude of the responce.Poles are what make the system stable or unstable...

Zeros in the right plane has same effect as a pole on a Phase characteristics, which is bad for stability.
Because of that you should always simulate both amplitude and phase characteristics.
 

what is GB.
i don't have the book but if you mean Z=0.1*ωc (ωc is cut off frequency of the system) then the author is designing a lag compensator.
the above equation is an estimation to decrease the improper phase behavior of lag compensator.
as we know the lag compensator increase the gain in low frequencies which is desirable but it also injects undesirable negative phase which decrease phase margin.
with the help of above estimation we pull this undesired negative phase from system's operating frequencies (about ωc) toward low frequncies.

finally thanks for donation.
 

Hi:

Thank you for the reply, is_razi.
GB, here, means the gain bandwidth product. So Z = 10*GB. According to the phase margin calculating equation given is this book:

Phase_margin = 180 - actan(w/|P1|) - actan(w/|P2|) - actan(w/Z)

when calculating the phase margin, w = GB, so make the compoent of actan(w/Z) is very small.


I think this case is opposite to the case of lag compensator. Does the author just want to minimize the effect of the Zero?
 

J,

Poles and zeros both affect the frequency response and time response. A pair of zeros on the jω (imaginary) axis produces a notch (zero gain) at the frequency ω.

For an exellent graphical description of the effects of poles and zeros on frequency response, go to **broken link removed**. This is the best intuitive presentation I've seen.

Regards,
K
 

hi agnivesh,
is this book available on edaboard.
 

I haven't searched it here, but most probably, you won't find this book here. You have to buy it or borrow it from your nearest library, if available.
ohterwise there are so many other books available.

(if u r from india, then u can easily buy very low price books on this + any subject from **broken link removed** . there are so many special indian price books which others pay around 10 times more money to buy. this particular book is costly even in this site.)

agnivesh
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top