while loop depending on input argument

[treehugger]

(cross posting)

now this is a very basic question:

The code seen below goes to infinite loop during synthesis, hence my sythesis tool halts (with an error like, "loop has iterated 64 times so i am halting blah blah"). The reason behind this is that "data" is assigned to X (undefined-unknown) and the evaluation (i<data) yields X, and a while loop executes if its condition is X.

Isn't this an apparent problem? Am i missing some point? What is the workaround?


module example(data, trig)

input [4:0] data;
input trig;
output out;
reg out;
integer i;

always @ trig
begin

out=0;
i=0;
while(i<data)
begin
out=~out;
end

end

endmodule


I just need a loop which runs until it hits a variable number given by the user, not until a constant predefined value..

How to?

 

[haytham]

hi
While loop is not synthesiable
Please re-write your code using synthesiable conditional statement

thanks

 

[treehugger]

hi
While loop is not synthesiable
Please re-write your code using synthesiable conditional statement

thanks

can show me a source stating that while loops are not synthesiable?

indeed, if while loops were not synthesiable my synthesis tool would generate an error message stating that "it is not supporting while loops and it is not synthesiable". but i do not get such an error message. i get an error message stating that "the loop is not finite".

 

[tkbits]

To the synthesizer, a while loop is a macro loop. The number of repetitions must be known at synthesis time.

Keep in mind that you are describing digital logic. Digital logic is not a computer - it does not have "instructions" that are "executed".

You implemented a counter as a variable. In digital logic, one implements a counter device that you can start and stop with control signals.

A free-running counter that doesn't stop looks like this:

register [4:0] i;

always @(posedge clk)
begin
    i <= i + 1;
end

It will "wrap around" when it reaches its maximum value. The clk signal will determine how fast the counter will count. To this basic counter, you add "sequential code" to set what conditions the values will change under, and what values they will change to. In synthesis, "sequential code" is not "sequenced"!

 

[haytham]

Hi
I am working in the field of digital design for about four years now.
I saw different designs
I did never see a while loop used in the RTL because as said in a previous post Hardware is different than Software because the synthesis tool should know the size of hardware at synthesis time.

In digital world, never use while loop in making yuor design hardware. Use it in Test benches only

This is an advice, take it or leave it

Welcome in the hardware world.

Thanks
Haytham