Which Verilog functions can be synthesized in Synthesis?

[choonlle]

casex,casez,wand,triand,wor,trior,real,disable,forever,arrays,memories,repeat,task, while –some are accepted by synthesis tools.

--That’s means, we cannot confirm whether above syntax, can be synthesis in synplify. So, how we can determine it?

by,
choonlle

 

[nand_gates]

Re: Problem:Verilog Code

Every Synthesis tool comes with document which tell what is supported
and what is not from HDL. It also includes better RTL coding guidelines.
So search for the doc and read it first before you even start writing the RTL.

 

[snake_eyes]

Re: Problem:Verilog Code

Any good verilog book shall give the list of synthesisable and non-synthesisable language functions/syntax.
The systhesis tool document also has the list.
The best reference is verilog reference manual whihc would clearly explain this issue.

 

[caplash_vlsi]

Re: Problem:Verilog Code

i think it is better to read the reference manual of the tool u want to use rather than lrm because every tool comes with different features and different synthesizable capabilities........so go through the manual of synplify to clarify ur doubts