which verilog code is better for counter?

[digi001]

here is 2 different textbooks show a counter. is one any better than the other, or do both end up being synthesized the same way?

	// Reset if needed, or increment if counting is enabled
always @ (posedge clk or posedge reset)
begin
	if (reset)
		count <= 0;
	else if (enable == 1'b1)
		count <= count + 1;
end

vs.

	// Reset if needed, or increment if counting is enabled
always @ (posedge clk or posedge reset)
begin
	if (reset)
		r_reg <= 0;
	else if (enable == 1'b1)
		r_reg <= r_next;
end

assign r_next = r_reg + 1;

 

[jwdonal]

I would expect that they would both synth the same way if you've got a good synth tool. But if they do synth differently I would expect the second version to generate some additional logic or possibly not be able to optimize as much. The first option is the most straight forward approach and how I always create a counter. The r_next in the second version is a redundant assignment - there is no need to have it, it would be more clear just to say r_reg <= r_reg + 1; which would then be equivalent to the first option.