Thanks,
How do we measure jitter of PLL(lock condition){I mean before fabrication }. I could measure jitter of a free runing VCO using cadence-spectre tool.
Honestly I don't do it. I do not have good enough (noise) models for my devices to be able to compare it to real thing.
But you can for sure do eye diagram. I guess you would obtain at least reference to which you can compare in case you do some changes.
I was never able to simulate jitter good enough to rely on it. But that's me.
it depends on the application , and system architecture of it
in the systems that require low phase noise it is prefered to use LC VCO
if the phase noise limitation not so strict , u can use ring specially it takes low area
on sillicon , and it is very simple to make it differential and get I , Q
in LC if u need I,Q u will need at least 4 spirals , which mean more area
1. Ring oscillators are normally used for low frequencies oscillation.
2. Phase noise in closed loop conditions can not be easily calculated. However, it can be approximated with some assumptions. One of a typical calculation for phase noise can be found in the paper “Prospects of CMOS Technology for High-Speed Optical Communication Circuits” by Razavi
Ring oscillators CAN work even at 5GHz in 0.13u process.
The problem is the generated noise of the VCO, so if one can afford BW large enough and not concerned about jitter transfer, I would definitely choose the ring oscillator.