Which tools can accept the same UPF?

[sun_ray]

The same UPF is accepted by modelsim and design compiler. How is it possible? What are the other tools that can accept the same UPF? The UPF consists of dome commands. Which tool vendor is the provider of such commands inside UPF?

 

[oratie]

Re: some queries for upf

There is a IEEE (not Synopsys) standard for UPF

IEEE 1801™ Standard for Design and Verification of Low-Power Integrated Circuits, the Unified Power Format (UPF)

So, different tools of different vendors may support it. For example, from Synopsys, it can be read by VCS (with MVSIM), MVRC, DesignCompiler, IC Compiler, Formlity, PrimeTime, PrimeRail.

Usually, the designer manually creates initial UPF for the design, than it can be read by DesignCompiler and after synthesis, the DC can write out the updated UPF. ICC can also write UPF. Still, initial UPF should be written manually (as well as RTL). Maybe there are some utilities, that can help you in creating initial UPF (as, I hope, there are such tools for helping in RTL coding).

 

[sun_ray]

Re: some queries for upf

There is a IEEE (not Synopsys) standard for UPF

IEEE 1801™ Standard for Design and Verification of Low-Power Integrated Circuits, the Unified Power Format (UPF)

So, different tools of different vendors may support it. For example, from Synopsys, it can be read by VCS (with MVSIM), MVRC, DesignCompiler, IC Compiler, Formlity, PrimeTime, PrimeRail.

Usually, the designer manually creates initial UPF for the design, than it can be read by DesignCompiler and after synthesis, the DC can write out the updated UPF. ICC can also write UPF. Still, initial UPF should be written manually (as well as RTL). Maybe there are some utilities, that can help you in creating initial UPF (as, I hope, there are such tools for helping in RTL coding).

Does the designer creates for verification only, when the designer manually creates the UPF? Or, he creates for both the verification and synthesis together? Is it after synthesis the UPF is automatically developed for PnR by synthesis tool?
What is the usual flow for developing the UPF?

Can you also please answer my related thread titled "for cutting power and rtl, verification methods"?

Thanks for the reply.

Regards

 

[oratie]

Re: some queries for upf

Designer creates single (it may source some other sub-UPFs) UPF, that will be used during all stages of design flow (verification, synthesis, PnR...).

After the synthesis (because, it may change the names of ... or any other modifications) DesignCompiler update the initial UPF and generate new UPF for PnR.

The usual flow of developing UPF - you should define power domains. Each instance of your design may present only in one domain. One domain differs from another: different voltage supply (one domain has 3.3V, another one has 3.0V - example); one domain may have power gating, while another may not have.

It is impossible to describe it here - you should find any manual (ask your tool vendor).

Synopsys supported implementation flows are:
 In Design Compiler (enabled by Power Compiler), additional low-power circuit structures
are defined or created based on the directives of the UPF commands. A refined UPF file will
also be generated to accompany the generated netlist.
 Even for a fully-connected PG netlist, the accompanying UPF file will still contain all the
required information to reconstruct the low-power circuit structures.
 Simulation tool can read both the netlist and the accompanying UPF side-file (netlist + UPF)
to correctly model the complete circuit structures including the low-power structures.
 Formal Verification tool will perform comparison between two netlist + UPF circuit
descriptions.
 Optionally, a fully-connected PG netlist can be used, solely, in place of the netlist + UPF as
an input to a verification tool (simulation or formal verification).
 In IC Compiler, physical implementation and floor-planning constraints can be applied, thus
further refining the low-power circuits.
 IC Compiler will have the options of generating a purely logical netlist or a fully connected
PG netlist. A refined UPF side-file will also be generated to accompany the generated netlist.
 A netlist + UPF circuit description must always be used together as an input to the
implementation tool, such as Design Compiler or IC Compiler.

 

[sun_ray]

Re: some queries for upf

oratie

Can you please let me know which tool is used for doing quality or lint check for the upf. Is it done by spyglass?

Regards

 

[oratie]

Re: some queries for upf

DesignCompiler during execution of "load_upf" command performs lint check (as well as ICC doing during UPF reading). I think, that the other tools also perform lint check during UPF loading. Of course, before loading UPF in DesignCompiler, you should have already loaded RTL code.

 

[sun_ray]

Re: some queries for upf

But are lint checking tools like spyglass used for checking UPF?

 

[englishdogg]

to my understanding for UPF - synopsys MVRC is used as a lint check for UPF

 

[dave_59]

We have a video seminar on UPF integration with Questa: https://verificationacademy.com/res...d/poweraware-verification-upf-tips-and-tricks.

BTW, Modelsim does not read UPF, but the next level up product, Questa, does.

Dave

 

[sun_ray]

What about spyglass?

 

[englishdogg]

yes, to my knowledge spyglass has some infrastructure to read UPF