Which tool can generate VLSI layout from VHDL code?

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lithium

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Hi,
I wanted to know which tool is capable of generating a VLSI layout if a VHDL code is supplied?

Some documentation about this would be helpful.

I know that such tools would not be free, but if anyone knows something similar tool, it'd be great.

regards,
Lithium.
 

I believe that there is not 1 tool that can convert VHDL to layout. You would need more than one to do this job. You would need something for synthesis and something for place and route.
 

you should convert VHDL to gate list first, and then P&R
 

yes , one of my friends use mentro tools to do this
frist use leonardo for synth.
then use place and route in IC station to do the job , but u need the cells library of the process u use
 

There are many steps between VHDL code & VLSI layout that must be go thru. And each step may require one tool.
 

Hi gentle_man & khouly,

so u mean to say that first i convert the VHDL code to gate level using a tool like leonardo. then use place & route tool of the vlsi layout software to get the required layout?

also the cell library which u mentioned. i use tan*ner l-edit, s-edit ,etc. we have a standard cell library in school. would these be wnough considering the gate level wouldnt be too complex to have a professional standard cell library?

thanx for all your replies, i really appreciate it.

regards,
Lithium.[/quote]
 

hi lithium
i donot know if tanner can do this job or not
 

maybe you mean 'physical synthesis', but it cann't do final layout.
 

I think what you need were some tools adopted "silicon compiler" technique. But the technique isn't still ripe.
 

Hmm. If you look for "one tool" there is nothing like this. But the closest to your requirement is Magma BlastRtl, BlastFussion.
 

Hi guys,
was just wondering...
can i use a tool to get a gate level or even switch level functional diagram of the VHDL code. i think leo*nardo would do it.

once i have this, i can use the place & route tools in the VLSI layout editor to build the necessary layout.

wanted to know if this is the right approach or is there something im not considering at all?

regards,
Lithium
 

search rtl2gds in the board or www.
 

can anyone suggest appropriate method/steps to design the layout from vhdl code.....
 

Hi all,

Here is the flow from RTL to GDSII:

1 - RTL code is written (hand or generated through automatic tools) (VHDL/Verilog ...)

2 - Then RTL simulations are done to check if RTL is functional. (NCSim, VCS, ...)

3 - Then synthesis step comes, which converts RTL netlist into gate level netlist. (Synopsys Design Compiler)
- Constraints are added at this step
- STA is done to ensure design meets timing (Synopsys Prime Time)

4 - DFT is inserted & related constraints added (Synopsys DFT Compiler, Synopsys Tetramax)
- STA done again (Synopsys Prime Time)

5 - Netlist is delivered to backend tool (PR tool) (Synopsys ICC, Magma Blastfusion, Cadence SOC Encounter, ...)

6 - Gate level netlist is exported from backend tool

7 - Final verification steps are done
- Physical verification (DRC/LVS) (Mentor Calibre, ...)
- Extration, Delay Calculation, STA (Synopsys RC Extract, Synopsys PrimeTime, ...)
.........

8 - Design is sent to fab

Best regards,
Gokhan
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Last edited:

Hi ,

there is a tool called Alliance which can convert the vhdl code to layout.....I think this tool is a free and open source tool...
 
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    Richm

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thank you yo all
alliance is based on linux mode or window mode????
 

Alliance is based on linux mode....
 
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    Richm

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