Which one should I learn, VHDL or Verilog?

[magnetra]

Which one should I learn, VHDL or Verilog?

 

[jelydonut]

Re: Verilog or VHDL

Well it wouldn't hurt to know both.. I personally perfer verilog.. but thats mostly cause im lazy and don't like to type much..

Its more important that you understand what your hdl will synthesize to then just knowing a language..

No matter which language you choose make sure to read the "Verilog/VHDL Synthesis Primer" both by Bhasker.. i think.. Also, the reuse methodology manual has a couple of important chapters on RTL coding style, etc.

jelydonut

 

[magnetra]

Re: Verilog or VHDL

Any good place on the net for beginners?

Magnetra

 

[xysafety]

Re: Verilog or VHDL

http://www.sunburst-design.com/papers/
**broken link removed**

 

[subgrid]

Re: Verilog or VHDL

Verilog is easy learned !

 

[emadi]

Re: Verilog or VHDL

verilog is more advanced from vhdl

 

[s2c97]

Re: Verilog or VHDL

This question has been asked very quite often in previous post. You should make a search, and I'm sure you will get a lot of hits on that question.

 

[z81203]

Verilog or VHDL

someone said to me for asic verilog better, for fpga try vhdl. but i like verilog.

 

[duet12]

Verilog or VHDL

Verilog is more "free-style" and easier to learn. VHDL is a stricter language. Verilog is widely used in North America, whiel VHDL is more popular in Europe.

 

[jetset]

Re: Verilog or VHDL

verilog is more advanced from vhdl

hum why do you think so?

 

[Manjunatha_hv]

Re: Verilog or VHDL

It is an old topic or debate...go through thr RULES



If you learn one language then the other one becomes very easy...

for example if you learn VHDL then it is matter of couple of days to understand Verilog....

Verilog widely used in the industry, it is very powerful language for verification,
it is easy to learn..if you know C prog...

Where as VHDL very decriptive language ...but very powerful for synthesis of circuits...


---manju---

 

[yangxh]

Verilog or VHDL

Maybe both is OK.For me I think Verilog is easy to learning and convenient for understanding.

 

[sp]

Verilog or VHDL

i love this words...

Verilog widely used in the industry, it is very powerful language for verification,
it is easy to learn..if you know C prog...

Where as VHDL very decriptive language ...but very powerful for synthesis of circuits...

it say wad i wanna mention...but problems wth expressing myself...

in my experience... when i write VHDL i see the hardware as i write...

and this is not true wth C language type...

regards,
sp

 

[emi_engr]

Re: Verilog or VHDL

verilog is better for professionals.

 

[hakeen]

Re: Verilog or VHDL

Well two basic things:

-Your geographical place: If you re in America, you should know Verilog is popular there. If you re in Europe, here they usually prefer VHDL. So for job's point of view, you should consider these facts.

-Structure: Verilog looks like basic programming languages (e.g. Basic, Assembly etc.). However, VHDL looks like higher level and easy to understand due to its close structure to a normal spoken language (i.e. English).
PS. These ideas look like foolish, but how I think about these languages...

Ciao

 

[newbiebk]

Re: Verilog or VHDL

i think you should study VHDL

 

[avimit]

Verilog or VHDL

VHDL if you want to develop hardware. Verilog cannot do very simple things as writing a generic function. So its pretty useless for RTL.

 

[anan_tv]

Re: Verilog or VHDL

Haiii all,


Let me join the discussion of VHDL Vs Verilog.

So far I have involved in two FPGA & one ASIC designs (front end)

One FPGA & ASIC designs in Verilog => very easy for writting & friendly syntaxes like C.

One FPGA design in VHDL ==> Very easy to imagine the Hardware components while writting RTL & simulation.

Have a look at the attached document for table of differences.