Which one should I learn today? Verilog or Systemverilog?

[electronicslab]

Which one should I learn today? Verilog or Systemverilog?

 

[danadakk]

This might help -

Verilog vs. SystemVerilog: What are the Differences Between Them?

What is the Verilog? FPGA series like Zynq-7000 SoC, Kintex-7 FPGAs, FPGA Spartan-7, and so on refer to a type ... Read More

circuitdiagrams.in

Regards, Dana.

 

[FvM]

SystemVerilog is an extension of Verilog, recent hardware design and verification tools are usually configured for SV support even if you are compiling standard Verilog designs. You'll start learning with basic Verilog constructs and proceed to SV specific elements if they help to improve your code.

In 2009, the Verilog standard (IEEE 1364-2005) was merged into the SystemVerilog standard, creating IEEE Standard 1800-2009. Since then, Verilog has been officially part of the SystemVerilog language. The current version is IEEE standard 1800-2023

https://en.wikipedia.org/wiki/Verilog

 

[sky_siliconthink]

Maybe begin with verilog and migrate to systemverilog.
For synthesizable RTL, just a little difference (the understanding of hardware architecture is the same). systemverilog is a good choice for design verification. You can search for "UVM" methodology.

A good introduce of verilog: https://www.udemy.com/course/icfpga...rification/?referralCode=6C6E0AFD06C1B3C76515