which one is the most important

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hello！！
i am a new learner in digital logic design, and i want to know "verilog" and "vhdl"
which is most in digital design or both ??
 

verilog very easy for beginners
if he know c or any basic computer language.
 

verilog/vhdl both r easy to learn if u know any of the prgming languages. comparitively verilog is much easier to code than vhdl.
 

Verilog is easy to learn but complicated while designing than vhdl designs, once u learn vhdl its very easy to design, many features in vhdl
 

As they both exist today, it proves they are both important. Indeed verilog is easy to learn and easy to use. But vhdl is not very hard so as not to learn. In my opinion, I suggest that it is better for you to learn vhdl because it is supported by most of industrial softwares.
 

VHDL is older and very easy to learn, but you need to buy a good book or find simple tutorials to start with.

with time you will be convinced that VHDL gives you a better imagine and well organised hierarchy of your designs.

good luck
 

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