Jan 6, 2014 #1 S snlaron Newbie level 4 Joined Jan 6, 2014 Messages 5 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 28 which of the == or === operator is synthesizable in verilog?
Jan 6, 2014 #2 D dave_59 Advanced Member level 3 Joined Dec 15, 2011 Messages 843 Helped 366 Reputation 736 Reaction score 361 Trophy points 1,353 Location Fremont, CA, USA Activity points 7,477 Re: verilog operator,which of the == or === operator is synthesizable in verilog? Both. However you use === when you want to compare with X or Z, and that is not synthesizable.
Re: verilog operator,which of the == or === operator is synthesizable in verilog? Both. However you use === when you want to compare with X or Z, and that is not synthesizable.
Jan 7, 2014 #3 S snlaron Newbie level 4 Joined Jan 6, 2014 Messages 5 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 28 Re: verilog operator,which of the == or === operator is synthesizable in verilog? dave_59 said: Both. However you use === when you want to compare with X or Z, and that is not synthesizable. Click to expand... Thank you sir. Since X or Z are not snythesizable , === is not snythesizable?
Re: verilog operator,which of the == or === operator is synthesizable in verilog? dave_59 said: Both. However you use === when you want to compare with X or Z, and that is not synthesizable. Click to expand... Thank you sir. Since X or Z are not snythesizable , === is not snythesizable?
Jan 7, 2014 #4 D dave_59 Advanced Member level 3 Joined Dec 15, 2011 Messages 843 Helped 366 Reputation 736 Reaction score 361 Trophy points 1,353 Location Fremont, CA, USA Activity points 7,477 Re: verilog operator,which of the == or === operator is synthesizable in verilog? if (A === 0) is functionally equivalent to if (A == 0) and both are synthesizable. However, some synthesis tools may choose not to support it.
Re: verilog operator,which of the == or === operator is synthesizable in verilog? if (A === 0) is functionally equivalent to if (A == 0) and both are synthesizable. However, some synthesis tools may choose not to support it.
Jan 7, 2014 #5 S snlaron Newbie level 4 Joined Jan 6, 2014 Messages 5 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 28 Re: verilog operator,which of the == or === operator is synthesizable in verilog? Thank you again sir. can you name some synthesis tools that can synthesize === operator?
Re: verilog operator,which of the == or === operator is synthesizable in verilog? Thank you again sir. can you name some synthesis tools that can synthesize === operator?
Jan 12, 2014 #6 S snlaron Newbie level 4 Joined Jan 6, 2014 Messages 5 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 28 Re: verilog operator,which of the == or === operator is synthesizable in verilog? dave_59 said: if (A === 0) is functionally equivalent to if (A == 0) and both are synthesizable. However, some synthesis tools may choose not to support it. Click to expand... Thank you again sir. can you name some synthesis tools that can synthesize === operator?
Re: verilog operator,which of the == or === operator is synthesizable in verilog? dave_59 said: if (A === 0) is functionally equivalent to if (A == 0) and both are synthesizable. However, some synthesis tools may choose not to support it. Click to expand... Thank you again sir. can you name some synthesis tools that can synthesize === operator?