Which memory to choose for CPLDs

Hello everyone,

I am planning to use a Xilinx CPLD, probably the XC2C32A 100VQ but I cannot understand how to connect an I2C or SPI flash to store the logic. Any help?

Thanks,

Mush

mush said:

Hello everyone,

I am planning to use a Xilinx CPLD, probably the XC2C32A 100VQ but I cannot understand how to connect an I2C or SPI flash to store the logic. Any help?

Thanks,

Mush

Click to expand...

you should develop program revelant to i2c or spi protocol communicating with flash.

Basically, do I need an external flash or the CPLD contains a FLASH to store the logic? I know that FPGAs need an external flash but what about the CPLDs?

i mistake your first post. Generally CPLD need not external FLASH. the best way is to see datasheet of your CPLD.

CPLD do not need external flash to store it image only FPGA need external flash.

I had a look in the datasheet and the configuration files ds090, ds093 but I couldn't find any information about the memory. I have to configure a number of registers in an ASIC (about 370 of 8bits its). If the CPLD contains a flash memory is it enough to store both logic and cofiguration registers? If I have to use an external flash which solution is better for an on board programming? A JTAG programmed FLASH?

The CPLD does not contain any flash or any kind of memory. It is a basically a part for creating random combinational or sequential logic. You can store stuff in registers but that's the extent of "storage". You'll have to add external flash if you want to store register values for an ASIC. If you connect all the pins of the flash to the CPLD you can program the flash using the JTAG of the CPLD (boundary scan). I've seen a number of companies that produce tools that will generate SVF files for programming SPI flash in circuit. As SPI flash is a commodity product it will be significantly cheaper than a specialty part like: http://www.atmel.com/devices/AT18F010.aspx

Regards

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Have you considered using something other than a CPLD like: http://www.microsemi.com/products/fpga-soc/fpgas?

If you use an actual FPGA like a ProASIC3 nano you can get storage and enough logic to build whatever else you need in the device. These parts are pretty cheap and they're reprogrammable as their configuration is eeprom based they are instant on.

Regards

It looks a good solution! No use of extra flash,low power consumption and low price. Do you know if it can be progrmmed with ISE and DLC10 cable of Xilinx? I will have a detailed look tommorow .

Regards

They have their own programming pod, of course it's still a JTAG pod so you might be able to program the parts using an SVF file generated out of their tools and send it through the Xilinx pod. Last time I used the parts we borrowed a pod from another group and later in production we had the parts pre-programmed for us.

Regards

CPLD can store your registers value. Once you programed CPLD, those value can not be changed. how many registers does CPLD store depend on the size of CPLD.

seesea11 said:

CPLD can store your registers value. Once you programed CPLD, those value can not be changed. how many registers does CPLD store depend on the size of CPLD.

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mush said:

I have to configure a number of registers in an ASIC (about 370 of 8bits its).

Click to expand...

The OP is going to need a pretty big CPLD to store those register values, 2960-bits just for the storage and more for their control logic. Besides have you priced the big CPLDs lately, they are usually expensive as they are mostly still at older technology nodes, not much of a market for die shrinking them to reduce their cost. That's why I suggested using something like a Microsemi ProASIC3 part, which is still under active development, unlike most CPLDs, which seem to be more like abandon-"hard"-ware than actively being developed.

Regards

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mush,

You should also check out the iCE40 family from Lattice Semiconductor, it's got memory too and it's meant for portable applications so it's got incredibly low power and it's very low cost.https://www.latticesemi.com/en/Products/FPGAandCPLD/iCE40.aspx

Regards

Another question. Isn't necessary for the pins of CPLD to be open drained to implement the I2C?

Just use an active low output enable tri-state driver with output signal connected to both the drivers input and enable.

Regards

Another question. Isn't necessary for the pins of CPLD to be open drained to implement the I2C?

Click to expand...

I don't know a CPLD that doesn't offer the feature. Even a GAL16 with 8 macro cells has it...

Yes you are right, it has the opporunity!

Thanks