imbichie
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Hi all,
Please check the below two verilog codes and please let me know, whether the hardware implementation of both codes are same or not?
If not same which is the better logic.
Logic 1:
Logic 2:
The logic of the codes is like this, under active low rst the value of a is low and when the b is high the value of a became low in the first clock and became high in the 2nd clock. (The behavior of signal b is like this : whenever the b is high, its high for even number of clock, means b can be high for continuously either 2,4,6,8,...2n etc clock cycles ).
Please check the below two verilog codes and please let me know, whether the hardware implementation of both codes are same or not?
If not same which is the better logic.
Logic 1:
Code:
always @ (posedge clk or negedge rst)
begin
if (~rst)
a <= 1'b0;
else if (b)
a <= ~a;
endLogic 2:
Code:
always @ (posedge clk or negedge rst)
begin
if (~rst)
a <= 1'b0;
else if (b && ~a)
a <= 1'b1;
else
a <= 1'b0;
endThe logic of the codes is like this, under active low rst the value of a is low and when the b is high the value of a became low in the first clock and became high in the 2nd clock. (The behavior of signal b is like this : whenever the b is high, its high for even number of clock, means b can be high for continuously either 2,4,6,8,...2n etc clock cycles ).