VHDL is the VHSIC Hardware Description Language. VHSIC is an abbreviation for Very High Speed Integrated Circuit. It can describe the behaviour and structure of electronic systems, but is particularly suited as a language to describe the structure and behaviour of digital electronic hardware designs, such as ASICs and FPGAs as well as conventional digital circuits.
VHDL is a notation, and is precisely and completely defined by the Language Reference Manual ( LRM ). This sets VHDL apart from other hardware description languages, which are to some extent defined in an ad hoc way by the behaviour of tools that use them. VHDL is an international standard, regulated by the IEEE. The definition of the language is non-proprietary.
VHDL is not an information model, a database schema, a simulator, a toolset or a methodology! However, a methodology and a toolset are essential for the effective use of VHDL.
Simulation and synthesis are the two main kinds of tools which operate on the VHDL language. The Language Reference Manual does not define a simulator, but unambiguously defines what each simulator must do with each part of the language.
VHDL does not constrain the user to one style of description. VHDL allows designs to be described using any methodology - top down, bottom up or middle out! VHDL can be used to describe hardware at the gate level or in a more abstract way. Successful high level design requires a language, a tool set and a suitable methodology. VHDL is the language, you choose the tools, and the methodology... well, I guess that's where Doulos come in to the equation!
Verilog is a Hardware Description Language; a textual format for describing electronic circuits and systems. Applied to electronic design, Verilog is intended to be used for verification through simulation, for timing analysis, for test analysis (testability analysis and fault grading) and for logic synthesis.
The Verilog HDL is an IEEE standard - number 1364. The standard document is known as the Language Reference Manual, or LRM. This is the complete authoritative definition of the Verilog HDL.
IEEE Std 1364 also defines the Programming Language Interface, or PLI. This is a collection of software routines which permit a bidirectional interface between Verilog and other languages (usually C).
One important note: Don't confuse Verilog HDL with the Verilog-XL family of simulators. In the mid-80's, Gateway Design Automation developed a logic simulator, Verilog-XL, to simulate designs described using their proprietary Verilog HDL. Cadence have since bought Gateway and retained the Verilog-XL simulator, but the language, Verilog HDL, is now maintained by Open Verilog International (OVI). More on Verilog's history in the next Backgrounder article. In all of the pages on this Web site, when we refer to Verilog, we mean the HDL not the simulator.
Today, there is one and only one Verilog HDL. There are now many Verilog-related EDA tools available: formal verification tools, cycle-based simulators, logic synthesisers, timing analysers and ESDA design entry tools with Verilog support. There are of course slight differences between these tools in the aspects of the Verilog HDL that are supported. Not all simulators support the full Verilog HDL, for example.
Finally, VHDL is not an abbreviation for Verilog HDL - Verilog and VHDL are two different HDLs. They have more similarities than differences, however.