Hvyikey
Newbie level 4
Hi,friends
I use tetramax to write out pattern file in two kinds, stil and v,that is write_patterns -f verilog_single_file or write_paterns -f stil . Now I want to verify whether the generated patterns are right or not and I simulate it by adding the verilog_single_file ,dut module ,library module and spf file to Modelsim. And these are my questions .
(1)Is there anything wrong with my idea ?
(2) what is the DPV testbench used for ? Is it use to verify the patterns ,too? What's the differnce between two ideas.
(3)When I use DPV testbench, which kind of pattern file should I use, -verilog_single_file or -stil.
Thanks .
I use tetramax to write out pattern file in two kinds, stil and v,that is write_patterns -f verilog_single_file or write_paterns -f stil . Now I want to verify whether the generated patterns are right or not and I simulate it by adding the verilog_single_file ,dut module ,library module and spf file to Modelsim. And these are my questions .
(1)Is there anything wrong with my idea ?
(2) what is the DPV testbench used for ? Is it use to verify the patterns ,too? What's the differnce between two ideas.
(3)When I use DPV testbench, which kind of pattern file should I use, -verilog_single_file or -stil.
Thanks .