I think, any CMOS logic would fit, depending on the voltage level it could be e. g. HCT (5V) or LVC (3.3V). But FPGA outputs have high drive capability, a buffer must not necessarily be used, except for driving higher voltages or to protect the FPGA, if the output is off-board.
If you are talking about clock fanout inside the FPGA, you can buffer the counter output with a BUFG primitive, or one of its relatives (see your ISE Libraries Guide). That global clock buffer drives a low-skew clock net throughout the FPGA.
If you are talking about clock fanout inside the FPGA, you can buffer the counter output with a BUFG primitive, or one of its relatives (see your ISE Libraries Guide). That global clock buffer drives a low-skew clock net throughout the FPGA.
Re: Which kind of buffer should I use for increasing the fan
Code:
Library UNISIM;
use UNISIM.vcomponents.all;
-- BUFG: Global Clock Buffer (source by an internal signal)
-- All Devices
BUFG_inst : BUFG
port map (
O => O, -- Clock buffer output
I => I -- Clock buffer input
);
-- End of BUFG_inst instantiation
here you will get info on all the resources available in given FPGA family and their usage and other howtos.(there are different directories for different families.