Which is the fasest logic for gray2bin convertor?

gray2bin

I'm designing async fifo 512x32 on virtex II and found that the criticial path is in gray2bin converter. Below is gray2bin function that i used, Do you know any faster logic?

function GRAY2BIN( GRAYSLV : std_logic_vector ) return std_logic_vector is
variable BINSLV : std_logic_vector(GRAYSLV'range);
begin
for I in GRAYSLV'range loop
if I = GRAYSLV'left then
BINSLV(I) := GRAYSLV(I);
else BINSLV(I) := GRAYSLV(I) xor BINSLV(I+1);
end if;
end loop;
return BINSLV;
end function GRAY2BIN;

gray2bin.c

Sorry. Actually, I need the fastest logic for gray counter. Traditional architecture is
1) gray2bin
2) binary increment
3) bin2gray

Does anyone know anyother technique?

Hope this helps....
https://www.dspguru.com/comp.dsp/tricks/alg/grayconv.htm

tut..

Hi,

try this :

--------------
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

Entity gray_cnt is
generic (
cnt_size : integer range 0 to 15 := 8
);
port(
rst : in std_logic ;
clk : in std_logic ;
cnt : out std_logic_vector (7 downto 0)
);
end gray_cnt;

architecture rtl of gray_cnt is

signal counter : std_logic_vector (cnt_size-1 downto 0);
signal tog : std_logic;
constant zero : std_logic_vector (cnt_size-1 downto 0) := (others => '0');


begin

grayrocess(clk,rst)
variable i : integer ;
begin
if (rst = '0') then
counter <= (others => '0');
tog <= '1';
elsif clk='1' and clk'event then
tog <= not tog;
if tog = '1' then
counter(0) <= not counter(0);
else
if counter(0) = '1' then
counter(1) <= not counter(1);
end if;
for i in 2 to (cnt_size-1) loop
if counter(i-1) = '1' and counter(i-2 downto 0) = zero(i-2 downto 0) then
counter(i) <= not counter(i);
end if;
end loop;
end if;
end if;
end process gray;

cnt <= counter;

end;


sucesfully synthesized with ise

:wink:

port
(
rst : in std_logic ;
clk : in std_logic ;
cnt : out std_logic_vector (cnt_size-1 downto 0)
);
end gray_cnt;

to BlackJack :

oops

if it's the only bug in my design, that's not too bad :wink: