Which is more susceptable to channel length modulation ... PMOS or NMOS?

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diarmuid

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In other words ... which has a lower output impedance in saturation - PMOS or NMOS?

According to Razavi, NMOS will have higher output impedance for given conditions. I
have seen this in sims but only marginally ... Rout(NMOS) is only slightly higher than
Rout(PMOS) in saturation.

Is this correct? If so why?

Thanks,

Diarmuid
 

Hi Diarmuid,
Channel Length modulation (LEMBDA) is process defined and is generally higher for PMOS compared to NMOS.
In other words ... which has a lower output impedance in saturation - PMOS or NMOS?
Click to expand...
Saturation resistance depends upon LEMBDA and Drain current. Drain current again is defined by mobility and W/L.
Since Mobility is more dominant than LEMBDA (this is aprox. same for PMOS/NMOS), NDMOS will give low impedance in saturation.
I don't know where you found Low ROn for NMOD in Razavi?
 
Hello,

Thanks for the quick reply. See below for my Razavi reference:

Ref: Design of Analog CMOS Integrated Circuits, Ch. 2, Section 2.4.5 Pg. 37:

"for given dimensions and bias currents, NMOS transistors exhibit a higher output resistance"

I guess he is referring to the case where we have a defined bias eg. common-source amp output stage. In this case Idsn = Idsp leaving the
only variable as lambda.

As you suggest ... lambda is generally higher for PMOS than NMOS which, for the situation with a defined bias, would give NMOS a higher output resistance compared to PMOS.

Would this be a correct way of thinking about things?

Also, why is lambda normally higher for PMOS than NMOS?

Thanks,

Diarmuid
 

diarmuid said:
... why is lambda normally higher for PMOS than NMOS?
Click to expand...

David M. Binkley "Tradeoffs and Optimization in Analog CMOS Design" contains a (lengthy) discussion on this: Chap. 3.8.4.1 (pp. 131 ff. in my edition). Lengthy, because channel-length modulation (CLM) cannot easily be separated from other competitive effects: vertical field mobility reduction (VFMR), and drain-induced barrier lowering (DIBL).

I think an essential contribution is the fact, that the equation for the Early Voltage VA (in a 1-D analysis, equs. (3.65) & (3.66)), which is a good measure for the longitudinal effects CLM & DIBL (excluding VFMR) is proportional to the square root of the bulk (i.e. channel) doping, which of course differs for NMOS & PMOS. This, however, would favour the PMOS because of its (usually, for p-substrate wafers) higher channel doping.
 
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Thanks Erikl,

Yes after some internet searching last night I ended up at this book. Fig.3.47 in particular indicates lambda to be higher in
general for PMOS.

Good looking book that. Think a trip to the bookshop this evening is in store

Thanks,

Diarmuid
 

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