Which FPGA family supports TMR components?

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delay

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TMR in FPGA

Hello,

Which FPGA family supports Triple Modular Redundancy components? Can TMR latches, flops be instantiated directly from the primitive/technology library of the supported device and its tool set? Further, what FPGA tools infer TMR devices upon synthesis?

delay (delay by technology)
 

Re: TMR in FPGA

TMR (Tripple Modulat Redundancy) technique is used to reduce SEU (Single Event Upset) in Space applications. Synplify tool automatically infers either C-C, TMR, or TMR_CC implementations in place of normal flip-flops, instead of post-processing the netlist for flip-flop substitution.

**broken link removed**
 

TMR in FPGA

Actel RT54SX family implements on silicon the TMR modules for flip-flops. It increases the consumption but make a rad tolerant design easier.
 

Re: TMR in FPGA

Check the Xilinx app notes they have a bunch of information on TMR.

They are also in beta with a tool called TMRtool that allows the user to select which parts of his circuit he wants to TMR since the penalty for TMR is about 3.2x in size and 10% in performance.

Also be aware that TMR is only good for the data path. In order to correct upsets in the configuration logic you must "scrub" the device at 10x the rate at which you expect an SEU.

Radix
 

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