wangkes
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a simple GGNMOS ESD at input.
VDD is 2.5V, and have no ESD protection with VSS.
I have seen the right circuit in some books. But I also seen
the left ESD circuit at a real chip.
Which is better ? I think the input wired to gate at left circuit, that is not good and sensitive.
But PMOS protection effect is less than nmos.
The W/L might be unsuitable. Thanks.
VDD is 2.5V, and have no ESD protection with VSS.
I have seen the right circuit in some books. But I also seen
the left ESD circuit at a real chip.
Which is better ? I think the input wired to gate at left circuit, that is not good and sensitive.
But PMOS protection effect is less than nmos.
The W/L might be unsuitable. Thanks.