irun2
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Hi all,
Can any one tell me which constraints written out by DC, like set_clock_latency/ set_clock_transition/ set_clock_uncertainty, will affect the clock spec generation in CTS stage?
The generated Clock.ctstch looks like below:
AutoCTSRootPin clkgen_m/u6/Z
Period 40ns
MaxDelay 0.01ns # sdc driven default
MinDelay 0ns # sdc driven default
MaxSkew 1600ps # sdc driven default
SinkMaxTran 200ps # sdc driven default
BufMaxTran 200ps # sdc driven default
Can any one tell me which constraints written out by DC, like set_clock_latency/ set_clock_transition/ set_clock_uncertainty, will affect the clock spec generation in CTS stage?
The generated Clock.ctstch looks like below:
AutoCTSRootPin clkgen_m/u6/Z
Period 40ns
MaxDelay 0.01ns # sdc driven default
MinDelay 0ns # sdc driven default
MaxSkew 1600ps # sdc driven default
SinkMaxTran 200ps # sdc driven default
BufMaxTran 200ps # sdc driven default