Whey posedge flops are added at starting of chain which starts with negedge flop

[Varun124]

Hi Team,

In Scan Insertion, one of the scenario to add the lockup latch posedge followed by negedge flops. But in 3rd party IP when they deliver if a chain has negedge flop, they add posedge flop. Will it not cause hold violation. If not do we need to take care anything spl like false path or ignore measure ?

Thanks in Advance

 

[BradtheRad]

Could there be a factor as to which output pin is used, whether Q or bar-Q? Certain events (or devices, or chain of devices) might need to wait the extra half-cycle.

Or another factor has to do with building the input stage from NAND gates versus NOR gates.
They behave in opposite manners regarding high or low pins, as to permitted idle condition, forbidden condition, etc.