In DC, when using set_clock_uncertainty to model the pre-layout clock tree , where can i get the info how much clock uncertainty should be assigned?
thanks !
---------- Post added at 13:50 ---------- Previous post was at 13:42 ----------
this link is from vendor of FPGA which is greatly different from asic for clock tree in FPGA has already been P&R. Could you plz give me a general description ?