where latches are used in ASIC design ?

Everywhere we are seeing posts on why latches should be avoided in a design. But I would like start a contrary thread which captures where and all latches are used in the present day ASIC design flow.
I am listing here few practical usage of latches in the ASIC design. I would like others to add to the list.

1. Latches are integral part of the clock gating cells
2. Lock up latches are used in the DFT flow to fix hold time violations in the scan chain

Some designers used double-latch instead one flop, that's allow to find "alway" a voltage where the design works, and some one said it is that consume less power.
That's made some problem for the scan insertion, the scan is not inserted by the tool, but in the RTL code...

hi rca, double latch in the place of a flop is usually inserted by the synthesis tools like DC or backend tools like SOC encounter. I am not sure on what basis the tools does that.

I have not seen any RTL engineer implementing a flop with double-latch in the RTL code.

latches are not only just used to fix hold for scan chain, but also in some function cases.
In my previous project, the hold violation is very hard to fix because of the setup and hold violation conflict.
Delay cell has so much difference in delay under ss and ff corners.
So we used the latch to fix the hold violation.

owen_li said:

latches are not only just used to fix hold for scan chain, but also in some function cases.
In my previous project, the hold violation is very hard to fix because of the setup and hold violation conflict.
Delay cell has so much difference in delay under ss and ff corners.
So we used the latch to fix the hold violation.

Click to expand...

owen_li, do you mean you met the time under slow corner but not under the fast corner ?

mr_vasanth said:

owen_li, do you mean you met the time under slow corner but not under the fast corner ?

Click to expand...

Yeah. In this case, hold violation is very huge. So If I tried to fix the hold, I should insert so many delay cells.
Coz delay cells will have much variation between ss corner and ff corner, so setup check will fail.
Using latch instead of delay cells will bring less variation, then hold violation will be fixed without affecting setup check.
Thanks!

HI
I would like to put some light on latches usage.

----------------------------------------------------
1. Latches are integral part of the clock gating cells
2. Lock up latches are used in the DFT flow to fix hold time violations in the scan chain
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1. Latches are not integral part of clock gating cells , clock gating cells are special kind of cells and logically one can think of one AND gate or OR gate used in clock gating.

2. Lock up latches used in DFT flow , it is correct and insertion of those latches happened when you tell tool to do so.
If you have more than one clock in design, then you can use lock up latches in scan chain where clock domain is changing.

Lock up latches are not normal latches, and if tool is inserting latches then there should not be any timing violations.

Latch based designs are fast and occupy less space if compared with Flops, but using latches will break STA. there will not be any timing analysis. So one using Latches in design should be knowing design very well.

That's why designer don't prefer to use latches in design , it could be a show stopper.

Rahul

Rahul,

Search for Integrated Clock Gating (ICG) cells in google. They contain latches and they are the one used by DC when you enable clock gating option during synthesis.

May I know how latches will break STA ? I believe STA tools make use of the time-borrowing or cycle stealing property of the latches and incorporate the latches in the timing anaysis.

Thanks .. I am will sure visit the ICG cells ..

STA basically work on edge basis , if you are using latch then STA tool will not have reference point to calculate timing on different path.

Rahul

For latches, STA has reference point of when latches becomes transparent and when it latch the data. For flip-flop data should be ready before the active edge of the clock, but for latches as it is transparent when the clk is active, data can arrive after the active edge. The trade-off here is the time available from latch to data is reduced if data arrive after active edge of the clock. So, it is borrowed time. STA is fully capable of calculating latch timing.

morris_mano said:

For latches, STA has reference point of when latches becomes transparent and when it latch the data. For flip-flop data should be ready before the active edge of the clock, but for latches as it is transparent when the clk is active, data can arrive after the active edge. The trade-off here is the time available from latch to data is reduced if data arrive after active edge of the clock. So, it is borrowed time. STA is fully capable of calculating latch timing.

Click to expand...

What about the cases where clock is not the enable signal for the latch ?

What about the cases where clock is not the enable signal for the latch ?

Click to expand...

The answer to that is similar to when data drives the CLK input of the flip flop. Driving data to CLK input is discouraged as STA will be difficult. You may have to define that data signal as clock and know how fast the data is changing and feed that to STA.

morris_mano said:

For latches, STA has reference point of when latches becomes transparent and when it latch the data. For flip-flop data should be ready before the active edge of the clock, but for latches as it is transparent when the clk is active, data can arrive after the active edge. The trade-off here is the time available from latch to data is reduced if data arrive after active edge of the clock. So, it is borrowed time. STA is fully capable of calculating latch timing.

Click to expand...

I dont agree with that. Data may change any time during active edge of clock , so it will be half of clock period where data can change any time. So if anyone using latches in design , must be sure about the data arrival.

How sta tool will take care that timing ? As I mentioned data may changed as any time during the active edge of clock , and this will create uncertainty in calculating timing for next path ...