Where can I get information to implement a PLL programmable clock in virtex 5?

[Cesar0182]

Greetings ... comment that I need to implement a programmable clock based on a PLL with ISE 14.5 for the Virtex 5 family (similar to the following example https://www.xilinx.com/support/documentation/application_notes/xapp888_7Series_DynamicRecon.pdf) but I cannot find information about the address map. Can someone help me with this please, thanks in advance

 

[gkram]

Greetings ... comment that I need to implement a programmable clock based on a PLL with ISE 14.5 for the Virtex 5 family (similar to the following example https://www.xilinx.com/support/documentation/application_notes/xapp888_7Series_DynamicRecon.pdf) but I cannot find information about the address map. Can someone help me with this please, thanks in advance

Please see chapter 2 of the following Xilinx document:

https://www.xilinx.com/content/dam/xilinx/support/documentation/user_guides/ug190.pdf

 

[FvM]

Xilinx support forum discussion suggests that Virtex 5 dynamic PLL reconfiguration doesn't work reliably http://forums.xilinx.com/t5/FPGA-Configuration/Virtex-5-PLL-ADV-dynamic-reconfiguration/m-p/965921

For Virtex-5 PLL, this is no longer supported. PLL may get mulfunction in some rare case.

It's suggested that you use DCM if possible and the changeable params would be M and D. You will need to find some other way to work around this if you must get a phase-shifted clock.

That's probably the reason why no Virtex 5 PLL reconfiguration address map is published.