when we use virtual clock for constaint in synthesis?

[drizzle]

virtual clock synthesis

hello all

in the multi-clock synchronous design synthesis, there will be virtual clocks for IO port constraints ,when we use it ?

can anyone expand more?

regards
drizzle

 

[phutanesv]

virtual clock in synthesis

Dear dude,


Virtual Clock is used for modelling I/O timing specification , based on what clock

the I/O pads are transfering data.

Phutane

 

[megastar007]

synthesis virtual clock

In multiclock domain, say block A is driving your block. Assume block A has different clock. since block A is driving IO pads of your block with respect to its clock,so we have to constrain your block inputs with block A clock. since your block doesnt have same clock input as block A you have to constrain using virtual clock.

hope this helps

 

[drizzle]

constraining virtual clock

Dear dude,


Virtual Clock is used for modelling I/O timing specification , based on what clock

the I/O pads are transfering data.

Phutane

But how can i know what clock the I/O pads are transfering data?

plz show me an example