when two signals in the sensitivity list switching at the same time, problem.

Hi, I'm new in verification. Here's the problem I need some help.
When two signals in the sensitivity list switching at the same time. It seems the simulator
would still consider one switched after another.
And if we have error detection in this block, sometimes it may trigger the error reporting
without a real error.
For example:

always @(*)
if (a)
if (b)
error;

when a:1->0 and b:0->1 at the same time, sometimes the error event will be triggered,
because the simulator may think that a switched after b (if I understand if correctly).
but this is not an error to us in the real world. Of coures more complicated combinational
logic would be involved in most of the time.
Since, I found myself having this problem regularly, I'm wondering is there an universal
and convenient way to solve it?
Many thanks.

In simulation, you will see the correct result, I means no wrong error and no missing error.
In VHDL you could see the delta cycle, and see error at wrong value but at the end of the time step, the result will be correct.