When there are violations in all areas of setup, hold, transition, cap, which one is recommended to start with fix_*_eco?

ECO is helpful to fix small pinpoint issues, it is not a good way to achieve timing closure. consider going back one step and executing physical synthesis again.

Collang2 said:

Is it better to fix all violations simultaneously (setup, hold, max transition, max cap...)?

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No, this is sure to become an endless runaway loop.

If you cannot step back to place and route, then this is the sequence i have followed before.
clock max cap, trans (lock the clocks down asap)
Then data max cap/ max trans
Then look at remaining setup violations. For the rest, this is helpful:

Qwerty112233 said:

No, this is sure to become an endless runaway loop.

If you cannot step back to place and route, then this is the sequence i have followed before.
clock max cap, trans (lock the clocks down asap)
Then data max cap/ max trans
Then look at remaining setup violations. For the rest, this is helpful:

View attachment 185763

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Thanks a lot!!
But I'm still wondering why you're encouraging it to go in this order.
Could you explain this or tell me the related data?

ThisIsNotSam said:

ECO is helpful to fix small pinpoint issues, it is not a good way to achieve timing closure. consider going back one step and executing physical synthesis again.

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Thank you! but, I am still beginner and i don't have the "Know-how & experience".

When I have Worst negative slack, Total negative slack, I don't know can i keep going or not. and i there is no one who can give me advice in person,,..
My design is not optimizing well from the CTS stage. (In Synthesis step, There is no violations.)

Collang2 said:

But I'm still wondering why you're encouraging it to go in this order.
Could you explain this or tell me the related data?

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Well my rationale for following this is intuitive:
Setup, hold, noise are all based on timing windows. So you fix all clock cap, trans violations first. Then you want realistic violations, so you need to fix max cap and max trans on data path. This ensures that you see realistic numbers. (Remember max cap and max transitions mean the timing data used from library is outside of the foundry characterized tables). So you fix these to get real timing picture.

Now setup and hold are two sides of coin and fixing one can worsen the other in some other scenario. Remember now, that setup fails can be mitigated even in Silicon. But hold can kill the chip. So you fix setup first completely.

And if it's a power critical chip, you should do leakage recovery after all setup is fixed, this will involve slowing some cells by VT swapping on the paths that show positive setup slack. This will automatically help hold since it slows down paths.

Then you move to hold fixing while keeping an eye on setup you create. Once both setup and hold are fixed then you check and fix any remaining noise (anything you touch before this point can cause noise )