When the package limits the bandwidth of an IC

Status
Not open for further replies.
R

rfmw

Advanced Member level 2
Joined
May 10, 2001
Messages
543
Helped
93
Reputation
190
Reaction score
51
Trophy points
1,308
Activity points
3,979
I am talking about (digital logic) packages in the (1-5) GHz range.

What do you think about different IC packages and its maximal operating frequency range? What the maximal useful frequency of SO-8, TSSOP-8, ...

Suppose we have SOIC-8 package. What is its typical pin capacitance and inductance? What about coupling between pins? Is TSSOP-8 a lot better choise for a couple of GHz bandwidth?

How do I fight against 1-2pF input (digital - ECL) pin capacitance? One way to lower the parasitics effects of an input pin (and thus improve return loss of termination) is to use as low transmission line impedance as possible.

Any other tricks? Ideas, app notes, documentation very welcome!

Regards,
rfmw
 

For > 2.5G BGA is the only conventional solution.
Pins of any kind of SMT package is too long, and internal
wirebonding make a lot of problems too.
BGA give the shortest way from silicon to PCB line
 

Can you give a rough estimation about BGA package parasitics (pin capacitance, inductance, pin to pin coupling, ...)?
 

BGA pin inductance is about 3-4 nH
 

Well 3-4nH is a lot! Perhaps the pin capacitance is low? With 4nH of pin inductance I can't imagine to get above 1Gbit/s data rate with this package...
 

You must add package parasitic inductor and capactor in spice netlist
and simulator to check it.
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…