[SOLVED] when the components value can be used?

[fahim1]

I want to use the components value inside my code,I found that the process gets component value in next clk.how can i fix that??I mean if i want the value of one component,the value calculated and used immediately in the same clock
thank you!

u1 : f1 port map (y, x ,a , clk);
signal a : std_logic_vector(3 downto 0);

process(clk)
begin
if (clk'event and clk='1')  then
p1 := a*b;

**a is the output of process

 

[sharath666]

Irrespective of whether a signal is generated from a component or from the same code it's usage remains the same. If a signal is generated in a particular clock cycle, then it can be used in the next cycle. In your case, if a is generated in clock 1, then p1 will be generated in clock 2. If that is not the case, then please post the waveform for further help.

 

[TrickyDicky]

If you draw the circuit you intend to create, you'll have a better time understanding what code you're writing.

 

[vGoodtimes]

@fahim1, My guess is that either:
1.) you don't want to use a clocked process to generate p1.
2.) you have 1 cycle of delay within a f1 component. This would be seen by looking at the code for the f1 entity. In that case, you would not want a clocked process to generate the output.